The present invention relates generally to audio accessory circuitry, such as circuitry for detecting actuation of pushbutton keys on a headset connected to a smart phone or the like. More particularly, the invention relates to accessory key detection circuitry that is capable of functioning in either the conventional analog “MSFT mode” or the conventional “digital communication mode.
Every headset used for mobile smart phone communication has a headset which has a microphone. The headsets for some mobile phones have a single pushbutton key, and other headsets may have 3 (or more) pushbutton keys. A typical headset has a microphone and 3 keys. When a headset key is depressed it sends a signal along a microphone conductor/line to the mobile phone. The mobile phone then recognizes that signal and performs a process or function corresponding to the depressed key, such as responding to the phone call, adjusting the audio volume, or muting the sound.
FIG. 1 shows a block diagram illustrating a conventional audio accessory key detection system which is capable of providing only conventional analog MSFT (“MicroSoft”) mode communication between (for example) a “host” such as a smart phone and an accessory such as a headset connected to the smart phone. The MSFT mode is a mode that is specified by various manufacturers (including Motorola, Nokia, HTC, and Samsung) in which accessory key detection circuitry contained in a headset detects/decodes actuation of 1 to 3 pushbutton headset keys that may be actuated to control functions such as audio volume control and audio muting. Corresponding circuitry in the smart phone receives a signal generated in the headset by actuation of a key and operates on that signal to perform the function corresponding to the depressed key.
In FIG. 1, audio accessory key detection system 1 includes a host circuit 2-1 and an accessory circuit 3-1. Host circuit 2-1 includes a microphone bias circuit 5 coupled by a conductor 6 and a resistor R1 to a microphone line/conductor 7. Resistor R1 may have a resistance of 2 kilohms. Host circuit 2-1 also includes an ADC (analog to digital converter) 9 having its input coupled to microphone line 7 and its output coupled by a digital bus 10 to a host controller 11. Accessory circuit 3-1 includes microphone and bias circuitry 13, which includes a microphone 13A and a bias circuit 13B coupled to microphone line 7. Microphone 13A and bias circuit 13B are connected in parallel between microphone line 7 and ground, and bias circuit 13B provides a bias voltage to microphone 13A. Accessory circuit 3-1 also includes three pushbutton keys or switches 15-1, 15-2, and 15-3. Switch 15-1 (i.e., “Key 1”) is connected between microphone line 7 and ground. Switch 15-2 (“Key 2”) is coupled between microphone line 7 and one terminal of a resistor R2 (which may have a resistance of 220 ohms) and one terminal of a resistor R3 (which may have a resistance of 390 ohms). A second terminal of resistor R2 is connected to ground. Switch 15-3 (“Key 3”) is coupled between microphone line 7 and the other terminal of resistor R3. If a user presses one of the keys of the accessory, a corresponding signal is transmitted by its accessory circuit 3-1 to host circuit 2-1, and host circuit 2-1 detects the transmitted signal and determines its meaning. (By way of definition, the term “depress” as used herein means “to press down on”, and the terms “press” and “depress” are used herein interchangeably to refer to pressing or depressing of a button or actuating of a pushbutton switch.)
Microphone bias circuit 5 typically includes a low noise LDO (low dropout voltage regulator) that establishes a low noise bias voltage on conductor 6. If Key 1 is depressed, the voltage on microphone line 7 is grounded. The bias voltage on conductor 6 is resistively divided by resistors R1 and R2 to generate a higher voltage on microphone line 7 if Key 2 of the headset is depressed. The bias voltage on conductor 6 is divided by means of resistors R1, R2, and R3 to generate an even higher voltage on microphone line 7 if Key 3 is depressed. Microphone bias circuit 5 may also include a low pass filter. The voltage generated on microphone line 7 by depressing one of keys 15-1, 15-2, or 15-3 is converted to a digital form by ADC 9, and host controller 11 determines from the resulting digital information on bus 10 which of the keys was depressed or released. ADC 9 and host controller 11 function together to discriminate between the three voltages that may be generated on microphone line 7, identify which of the three keys has just been either depressed or released, and cause the host to perform the desired operation.
FIG. 2 is a block diagram illustrating a known host and accessory system 20 which is capable of providing conventional digital communication (but not MSFT mode communication) between the host and its accessory headset. In FIG. 2, audio accessory key detection system 20 includes a host circuit 2-2 which includes a microphone bias circuit 5 coupled by a conductor 6 and resistor R1 to microphone line 7. Resistor R1 may have a resistance of 2 kilohms. Host circuit 2-2 also includes a host transceiver 21 having its input coupled to microphone line 7 and its output coupled by digital DATA_OUT bus 26 to an output of host controller 11. A DATA_IN bus 23 is coupled between an output of host transceiver 21 and a data input of host controller 11. In this example, host transceiver 21 includes a N-channel MOS transistor 25 having its source connected to ground, its gate connected to DATA_OUT bus 26, and its drain connected by microphone line 7 to the input of a buffer circuit 22 having its output connected to DATA_IN bus 23.
Audio accessory key detection system 20 also includes an accessory circuit 3-2 including microphone and bias circuitry 13 and N pushbutton keys or switches 15-1 (“Key 1”), 15-2 (“Key 2”), 15-3 (“Key 3”), 15-4, . . . 15-N. As in Prior Art FIG. 1, microphone and bias circuit 13 includes a microphone 13A and bias circuit 13B. Microphone 13A and bias circuit 13B are connected in parallel between microphone line 7 and ground, and bias circuit 13B provides a bias voltage to microphone 13A. Each of switches 15-1, 15-2, . . . 15-N is coupled between ground and a key detector and controller circuit 29. Key detector and controller circuit 29 is powered by a voltage supply signal VDD generated by an energy storage circuit 28, which may include a charge storage capacitor or a rechargeable battery. Energy storage circuit 28 in accessory circuit 3-2 is coupled between microphone line 7 and a reference voltage such as ground. Energy storage circuit 28 generates a supply voltage VDD on conductor 30, which provides operating power to key detector and controller 29. Key detector and controller circuit 29 generates a serial digital output signal DATA_OUT on serial data bus 36, which is connected to the gate of a N-channel MOS transistor 35 in accessory transceiver 31. The source of transistor 35 is connected to ground. The drain of transistor 35 is connected by microphone line 7 to the input of a buffer circuit 32 of accessory transceiver circuit 31. The output of buffer 22 produces a serial digital signal DATA_IN on serial data bus 33. DATAIN bus 33 is connected to an input of key detector and controller circuit 29.
Energy storage circuit 28 may include a storage capacitor CSTORAGE and a resistor connected in series between microphone line 7 and ground. VDD conductor 30 is connected to the junction between the resistor and one terminal of CSTORAGE, the other terminal of which is connected to ground. All of the energy required by accessory circuit 3-2 must be initially supplied to the storage capacitor by microphone bias circuit 5 of host circuit 2-2. Consequently, when there is data in the form of sequential “1”s and/or “0” being transmitted on microphone line 7, its voltage must be maintained at a high level (e.g., i.e., at approximately 2 volts) by microphone bias circuit 5 to ensure that energy storage circuit 28 remains adequately charged.
Key detector and controller circuit 29 requires very little current and power, and during data transmission energy storage circuit 28 may store added energy to power the integrated circuit chip in which host and accessory system 20 of FIG. 2 is fabricated. The energy is added because during data transmission the voltage on microphone line 7 successively switches between various “1” and “0” logic levels. The storage capacitor will be recharged during transmission of each “1” logic level, but not during transmission of “0” levels. Consequently, energy storage circuit 28 must store sufficient energy to be able to provide power for as long as any “0” level can be present on microphone line 7.
It would be very desirable to provide a single integrated circuit chip that is capable of being used for communication between a host circuit and an accessory circuit in either the MSFT mode or the digital communication mode.
Thus, there is an unmet need for a versatile, inexpensive integrated circuit to provide communication between a host circuit such as a smart phone and an accessory circuit such as an associated headset.
There also is an unmet need for a single integrated circuit chip that is capable of being used for communication between a host circuit and an accessory circuit in either MSFT mode or digital communication mode.